View S3C8625_4174233.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

product overview address spaces addressing modes control registers interrupt structure instruction set
S3C8625/c8627/c8629/p8629 product overview 1- 1 1 product overview sam8 product family samsung's sam8 family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu with a wide range of integrated peripherals, in variou s mask-programmable rom sizes. analog its major cpu features are : ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function the sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of six cpu clocks) can be assigned to specific interrupt levels. S3C8625/c8627/c8629/p8629 microcontroller s S3C8625/c8627/c8629/p8629 single-chip 8-bit microcontroller s are based on the powerful sam8 cpu architecture. the internal register file is logically expanded to incre ase the on-chip register space. S3C8625/c8627/c8629/p8629 contain 16/32 k bytes of on-chip program rom. in line with samsung's modular design approach, the following peripherals are integrated with the sam8 core: ? f our programmable i/o ports (total 27 pins) ? one 8-bit basic timer for oscillation stabilization and watchdog functions ? one 8-bit general-purpose timer/counter with selectable clock sources ? one 12 -bit counter with selectable clock sources, including hsync or csync input ? one interval timer ? pwm block with seven 8-bit pwm circuits ? sync processor block (for vsync and hsync i/o, csync input, and clamp signal output) ? ddc and normal multi -master iic-bus ? 4- channel a/d converter (8-bit resolution) S3C8625/c8627/c8629/p8629 are a versatile microcontroller s which are ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, pwm, sync signal processing, a/d converter, and multi-master iic-bus support with ddc. they are available in a 42- pi n sdip or a 44 -pin qfp package. otp S3C8625/c8627/c8629 microcontrollers are also available in otp (one time programmable) version named, s3p8629. s3p8629 microcontroller has an on-chip 32-kbyte one-time-programmable eprom instead of masked rom. s3p8629 is comparable to S3C8625/c8627/c8629, both in function and pin configuration except its rom size.
product overview S3C8625/c8627/c8629 /p8629 1- 2 features cpu ? sam8 cpu core memory ? 16/24/32 -kbyte internal program memory (rom) ? 464 -byte general-purpose register area instruction set ? 78 instructions ? idle and stop instructions added for power-down modes instruction execution time ? minimum 500 ns (with 12 mhz cpu clock) interrupts ? ten interrupt sources ? ten interrupt vectors ? seven interrupt level ? fast interrupt feature general i/o ? four i/o ports (total 27pins) 8-bit basic timer ? programmable timer for oscillation stabilization interval control or watchdog timer function ? three selective internal clock frequencies timer/counters ? one 8-bit timer/counter with several clock sources (capture mode) ? one 12-bit counter with h-sync and several clock sources ? one interval tim er pulse width modulator (pwm) ? 8-bit pwm: 7-ch sync-processor block ? vsync-i, hsync-i, csync-i input and vsync-o, hsync-o, clamp-o output pins ? pseudo sync signal output ? auto sog detection ? auto hsync polarity detection ddc multi-master iic-bus 1-ch ? serial peripheral interface ? support for display data channel (ddc1/ddc2b/ddc2bi/ddc2b+) normal multi-master iic-bus 1-ch ? serial peripheral interface a/d converter ? 4-channel; 8-bit resolution oscillator frequency ? 8 mhz to 12 mhz crystal operat ion ? internal max. 12 mhz cpu clock operating temperature range ? ? 40 c to + 85 c operating voltage range ? 4.0 v to 5.5 v package types ? 42-pin sdip, 44-pin qfp
S3C8625/c8627/c8629/p8629 product overview 1- 3 block diagram reset p1.0?p1.2 x in x out main osc internal bus p2.0 - p2.7 port 0 p0.0 - p0.7/int0 - int2 port 2 8-bit pwm (7-ch) sync- processor 8-bit counter (timer m0) port 1 pwm0 ? ? ? ? pwm6 vsync-i hsync-i csync-i vsync-o hsync-o clamp-o mt0cap 12 -blt counter (timer m1) mt1ck adc int0-int2 v dd , avref v ss1 , v ss2 test sam8 cpu i/o port and interrupt control 16/24 /32- kbyte rom 464-byte register file multi master iic-bus and ddc1/2b/2bi/2b+ interval timer (timer m2) p3.0?p3.7 port3 ad0 - ad3 multi master iic-bus scl1 sda1 scl0 sda0 figure 1- 1 . block diagram
product overview S3C8625/c8627/c8629 /p8629 1- 4 pin assignments p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p0.5/tm1ck p0.6 p0.7 p1.0/sda1 p1.1/scl1 v dd v ss1 x out x in test sda0 scl0 reset p1.2 p2.0/pwm0 p2.1/pwm1 S3C8625/ c8627/c8629 42-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0 / ad0 avref v ss2 p2.7/csync-i hsync-i vsync-i vsync-o hsync-o clamp-o p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 figure 1- 2 . S3C8625/c8627/c8629 42-sdip pin assignment
S3C8625/c8627/c8629/p8629 product overview 1- 5 p0.5/tm1ck p0.6 p0.7 p1.0/sda1 p1.1/scl1 v dd v ss1 x out x in test sda0 p3.2/ad2 p3.1/ad1 p3.0 / ad0 avref v ss2 p2.7/csync-i hsync-i vsync-i vsync-o hsync-o clamp-o p3.3/ad3 p3.4 p3.5 p3.6 p3.7 n.c. p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 n.c. p2.1/pwm1 p2.0/pwm0 p1.2 reset scl0 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 S3C8625/ c8627/c8629 44-qfp (top view) 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 figure 1- 3 . s3c8627/c8629 44-qfp pin assignment
product overview S3C8625/c8627/c8629 /p8629 1- 6 pin descriptions table 1-1. S3C8625/c8627/c8629/p8629 pin descriptions pin names pin type pin description circuit type sdip pin numbers shared functions p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 i/o general-purpose, 8-bit i/o port. shared functions include three external interrupt inputs and i/o for timer m0 and m1. selective configuration of port 0 pins to input or output mode is supported. d-1 d-1 d-1 d-1 d-1 d-1 d-1 d-1 1 2 3 4 5 6 7 8 int0 int1 int2 tm0cap tm1ck p1.0 p1.1 p1.2 i/o general-purpose, 3-bit i/o port. selective configuration is available for port 1 pins to input, push-pull output, n-channel open- drain mode, or iic-bus clock and data i/o. e-1 e-1 e-1 9 10 19 sda1 scl1 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 i/o general-purpose, 8-bit i/o port selective configuration of port 2 pins to input or output mode is supported. the port 2 pin circuits are designed to push-pull pwm output and csync signal input. d-1 d-1 d-1 d-1 e-1 e-1 e-1 d-1 20 21 22 23 24 25 26 32 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 csync-i p3.0?p3.3 p3.4?p3.7 i/o general-purpose, 8-bit i/o port selective configuration port 3 pins to input or output mode is supported. multiplexed for alternative use as a/d converter inputs ad0?ad3. d-1 e 35?38, 39?42 ad0?ad3 hsync-i vsync-i clamp-o hsync-o vsync-o sda0 scl0 i i o o o i/o i/o the pins are sync processor signal i/o, iic- bus clock, and data i/o. a a a a a g-3 g-3 31 30 27 28 29 16 17 ? v dd , v ss1 , avref, v ss2 ? power pins adc power pins ? ? 11, 12 34, 33 ? x in , x out ? system clock i/o pins ? 14, 13 ? reset i system reset pin b 18 ? test i factory test pin input 0v:normal operation,5v:factory test mode ? 15 ?
S3C8625/c8627/c8629/p8629 product overview 1- 7 pin circuits v ss v dd data output figure 1- 4 . pin circuit type a v dd noise filter 280 k w reset figure 1- 5 . pin circuit type b ( reset reset ) output v ss output disable data or other function digital input ttl input or adc input v dd figure 1-6. pin circuit type d-1
product overview S3C8625/c8627/c8629 /p8629 1- 8 typical 47-k w data output pull-up enable input open drain output disable v dd v ss v dd figure 1- 7 . pin circuit type e data output output disable input v ss open drain v dd figure 1- 8 . pin circuit type e-1
S3C8625/c8627/c8629/p8629 product overview 1- 9 data output input v ss figure 1-9. pin circuit type g-3
S3C8625/c8627/c8629/p8629 electrical data 19- 1 19 electrical data overview in this section, S3C8625/c8627/c8629 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ra tings ? d.c. electrical characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? i/o capacitance ? a /d c onverter electrical characteristics ? a.c. electrical characteristics ? input timing measurement points for p0.0?p0.2, tm0cap, and tm1ck ? oscillation characteristics ? oscillation stabilization time ? clock timing measurement points for x in ? schmitt trigger characteristics
electrical data S3C8625/c8627/c8629 /p8629 19- 2 table 19- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 type c (n-channel, open-drain) ? 0.3 to + 7.0 v v i2 all port pins except v i1 ? 0.3 to v dd + 0.3 output voltage v o all output pins ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 10 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current except port 3 + 100 sync-processor i/o pins and iic-bus clock and data pins + 150 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 19- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4. 0 v to 5.5 v) parameter symbol conditions min typ max unit input high voltage v ih1 all input pins except v ih2 and v ih3 0.8 v dd ? v dd v v ih2 x in 2.7 v dd v ih3 ttl input (hsynci, vsynci , and csynci) 2.0 v dd input low voltage v il1 all input pins except v il2 and v il3 ? ? 0.2 v dd v v il2 x in 1.0 v il3 ttl input (hsynci, vsynci , and csynci) 0.8 output high voltage v oh1 i oh = ? 8 ma ; port 3 only v dd ? 1.0 ? ? v v oh2 i oh = ? 2 ma ports 0, 2, clampo, h , and vsynco v oh3 i oh = ? 6 ma ; port 1
S3C8625/c8627/c8629/p8629 electrical data 19- 3 table 19- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 4. 0 v to 5.5 v) parameter symbol conditions min typ max unit output low voltage v ol1 i ol = 8 ma ; port 3 only ? ? 0.4 v v ol2 i ol = 2 ma port 0, 2, clampo, h , and vsynco 0.4 v ol3 i ol = 6 ma port 1; scl and sda 0. 6 input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 a i lih2 v in = v dd ; x out only ? ? 20 i lih3 v in = v dd ; x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v ; all input pins except x in , x out , and reset ? ? ? 3 a i lil2 v in = 0 v; x out only ? ? ? 20 i lil3 v in = 0 v; x in only ? 2.5 ? 6 ? 20 output high leakage current i loh1 v out = v dd ? ? 3 a output low leakage current i lol 1 v out = 0 v ? ? ? 3 a pull-up resistor r l1 v in = 0 v port s 3 .7?3.4 20 47 80 k w r l2 v in = 0 v reset only 150 280 480 supply current ( note ) i dd1 operation mode; 12 mhz crystal c1 = c2 = 22pf ? 15 30 ma i dd2 idle mode; 12 mhz crystal c1 = c2 = 22pf 5 1 0 i dd3 stop mode 1 10 a note : supply current does not include drawn internal pull?up resistors and external loads of output.
electrical data S3C8625/c8627/c8629 /p8629 19- 4 table 19- 3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2 ? 5.5 v data retention supply current i dddr stop mode, v dddr = 2.0 v ? ? 5 a notes : 1. during the oscillator stabilization wait time (t wait ), all cpu operations must be stopped. 2. supply current does not include drawn through internal pull?up resistors and external output current loads. v dd reset execution of stop instruction v dddr data retention mode stop mode reset occurs normal operating mode oscillation stabilization time t wait note : t wait is the same as 4,096 x x32 x 1/f osc . ~ ~ ~ ~ figure 19-1 . stop mode release timing when initiated by a reset table 19- 4. input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io
S3C8625/c8627/c8629/p8629 electrical data 19- 5 table 19-5 . a/d converter electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 4.0 v to 5 . 5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 8 ? bit total accuracy v dd = 5 v conversion time = 5 m s ? ? 2 lsb integral linearity error ile av ref = 5 v ? 1 differential linearity error dle av ss = 0 v ? 1 offset error of top eot 1 2 offset error of bottom eob 0.5 2 conversion time ( 1 ) t con 8 bit conversion 34 x n/f osc (3) , n=1,4,8,16 17 ? 170 m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss (4) ? v ss ? v ss v analog input current i adin av ref = v dd = 5 v ? ? 10 m a analog block current ( 2 ) i adc av ref = v dd = 5 v ? 1 3 ma av ref = v dd = 3 v 0.5 1.5 ma av ref = v dd = 5 v when power down mode 100 500 na notes : 1. " conversion time " is the time required from the moment a conversion operation starts until it ends . 2. i adc is an operating current during the a/d conversion. 3. f osc is the main oscillator clock. 4. v ss port shaves with the a v ss for S3C8625/c8627/c8629.
electrical data S3C8625/c8627/c8629 /p8629 19- 6 table 19-6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4. 0 v to 5.5v) parameter symbol conditions min typ max unit noise filter t nf1h t nf1l int0?2, tm0cap and tm1ck (rc delay) 300 ? ? ns t nf2 reset only (rc delay) 800 ? ? t nf1l t nf1h 0.8 v dd t nf2 0.2 v dd figure 19- 2. input timing measurement points for p0.0? p0.2, tm0cap, and t m 1ck
S3C8625/c8627/c8629/p8629 electrical data 19- 7 table 19-7 . oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit conditions min typ max unit main crystal or ceramic c2 c1 x in x out v dd = 4. 0 v to 5.5 v 8 ? 12 mhz external clock (main) x in x out v dd = 4. 0 v to 5.5 v 8 ? 12 mhz note : the maximum oscillator frequency is 12 mhz. if you use an oscillator frequency higher than 12 mhz, you cannot select a non-divided cpu clock using clkcon settings. that is, you must select one of the divide-by values. table 19-8 . oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 4. 0 v to 5.5 v) oscillator test condition min typ max unit crystal v dd = 4. 0 v to 5.5 v ? ? 20 ms ceramic v dd = 4. 0 v to 5.5v ? ? 10 external clock x in input h igh and l ow level width (t xh , t xl ) 25 ? 500 ns note : oscillation stabilization time is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is released. x in t xl t xh 1 / f x v dd - 0.5 v 0.4 v figure 19- 3. clock timing measurement points for x in
electrical data S3C8625/c8627/c8629 /p8629 19- 8 v dd v ss v out a b c d v in a : 0.2 v dd b : 0.4 v dd c : 0.6 v dd d : 0.8 v dd figure 19-4. schmitt trigger characteristics (normal port; except ttl input)
S3C8625/c8627/c8629/p8629 mechanical data 20- 1 20 mechanical data overview the S3C8625/c8627/c8629 microcontroller is available in a 42-pin sdip package (samsung part number 42- sdip-600) and a 44 -qfp package (samsung part number 44-qfp-1010b). note : dimensions are in millimeters. 42-sdip-600 14.00 0.2 0.50 0.1 39.10 0.2 0 ~ 15 0.25 +0.1 ? 0.05 #1 21 42 22 15.24 (1.77) 1.00 0.1 1.778 0.51min 3.50 0.2 3.30 0.3 5.08max figure 20- 1. 42-pin sdip package mechanical data (42-sdip-600)
mechanical data S3C8625/c8627/c8629 /p8629 20- 2 note : dimensions are in millimeters. 44-qfp-1010b 13.20 0.3 #44 (1.00) #1 13.20 0.3 0.35 +0.10 - 0.05 0.10 max 0~8 0.05 min 2.05 0.10 2.30 max 0.80 0.20 0.15 +0.10 - 0.05 10.00 0.2 10.00 0.2 0.80 figure 20- 2. 44-pin qfp package mechanical data (44-qfp-1010b)
S3C8625/c8627/c8629/p8629 ks88p6232 otp 21- 1 21 s3p8629 otp overview the s3p8629 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C8625/c8627/c8629 microcontrollers. it has an on-chip eprom instead of masked rom. the eprom is accessed by serial data format. the s3p8629 is fully compatible with the S3C8625/c8627/c8629, both in function and in pin configuration. because of its simple programming requirements, the s3p8629 is ideal for use as an evaluation chip for the S3C8625/c8627/c8629. p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p0.5/tm1ck p0.6 p0.7 sdat / p1.0/sda1 sclk / p1.1/scl1 v dd v ss1 x out x in v pp / test sda0 scl0 reset / reset p1.2 p2.0/pwm0 p2.1/pwm1 s3p8629 42-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p3.7 p3.6 p3.5 p3.4 p3.3/ad3 p3.2/ad2 p3.1/ad1 p3.0 / ad0 avref v ss2 p2.7/csync-i hsync-i vsync-i vsync-o hsync-o clamp-o p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 note: the bolds indicate an otp pin name. figure 21-1. s3p8629 pin assignments (42-sdip package)
ks88p6232 otp S3C8625/c8627/c8629 /p8629 21- 2 p3.2/ad2 p3.1/ad1 p3.0 / ad0 avref v ss2 p2.7/csync-i hsync-i vsync-i vsync-o hsync-o clamp-o p3.3/ad3 p3.4 p3.5 p3.6 p3.7 n.c. p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/tm0cap p2.6/pwm6 p2.5/pwm5 p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 n.c. p2.1/pwm1 p2.0/pwm0 p1.2 reset/ reset scl0 p0.5/tm1ck p0.6 p0.7 sdat /p1.0/sda1 sclk / p1.1/scl1 v dd v ss1 x out x in v pp / test sda0 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 s3p8629 44-qfp (top view) 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 note: the bolds indicate an otp pin name. figure 21-2. s3p8629 pin assignments (44-qfp package)
S3C8625/c8627/c8629/p8629 ks88p6232 otp 21- 3 table 21-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p1.0 sdat 9 (4) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p1.1 sclk 10 (5) i serial clock pin. input only pin. test v pp (test) 15 (10) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 18 (13) i chip initialization v dd / v ss1 v dd /v ss1 11/12 (6/7) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate 44-qfp otp pin number. table 21-2. comparison of s3p8629 and S3C8625/c8627/c8629 features characteristic s3p8629 S3C8625/c8627/c8629 program memory 32-kbyte eprom 16/24/32-kbyte mask rom operating voltage (v dd ) 4.0 v to 5.5 v 4.0 v to 5.5v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 42sdip, 44qfp 42sdip, 44qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p8629, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 21-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15?a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
ks88p6232 otp S3C8625/c8627/c8629 /p8629 21- 4 d.c. electrical characteristics table 21-4. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4. 0 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 a i lih2 v in = v dd ; x out only ? ? 20 i lih3 v in = v dd ; x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v ; all input pins except x in , x out , and reset ? ? ? 3 a i lil2 v in = 0 v; x out only ? ? ? 20 i lil3 v in = 0 v; x in only ? 2.5 ? 6 ? 20 output high leakage current i loh1 v out = v dd ? ? 3 a output low leakage current i lol 1 v out = 0 v ? ? ? 3 a pull-up resistor r l1 v in = 0 v port s 3 .7?3.4 20 47 80 k w r l2 v in = 0 v reset only 150 280 480 supply current ( note ) i dd1 operation mode; 12 mhz crystal c1 = c2 = 22pf ? 15 30 ma i dd2 idle mode; 12 mhz crystal c1 = c2 = 22pf 5 1 0 i dd3 stop mode 1 10 a note : supply current does not include drawn internal pull?up resistors and external loads of output.

▲Up To Search▲

Price & Availability of S3C8625

	To Download S3C8625 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .